A Phase Locked Loop (PPL) is an important module in an analog integrated circuit and a hybrid digital-analog integrated circuit, and is applied widely in fields such as wireless communication, frequency synthesis and clock recovery. A charge pump phase-locked loop (CPPLL) among various phase locked loops is widely applied to chip designs due to its high stability, wide capture range, and a digitized phase frequency discriminator.
The phase-locked loop is a feedback system in which a phase of an input signal is compared with a phase of an output signal.
FIG. 1 shows a structural diagram of a typical charge pump phase-locked loop system, which includes modules such as a phase frequency discriminator (PFD) 100, a charge pump (CP) 200, a loop filter (LF) 300, a voltage-controlled oscillator (VCO) 400 and a Multi-Modulus Divider (MMD) 500.
The CP 200 plays an important part in the system in that: the CP 200 converts a digital control signal output from the PFD 100, including a charging control signal UP and a discharging control signal DOWN, into an analog signal, and then controls an output frequency of the VCO 400 to realize a phase-locked function.
Here, the analog signal is required to have a small ripple and a good linearity degree. Thus, the CP 200 is required to meet two conditions that: a charging current and a discharging current are the same and are maintained constant within a certain range. In practice, the CP 200 has a serious current mismatch since due to limitations caused by undesired factors such as a channel modulation effect of MOS, a charge sharing and a charge injection, which is a main factor affecting the performance of the loop.
As shown in FIG. 2, a first existing charge pump circuit includes PMOS current mirrors MP1 and MP2, NMOS current mirrors MN2 and MN4, a PMOS switch transistor MP4, an NMOS switch transistor MN3, a bias circuit NMOS switch transistor MN5, output control signals from a phase frequency discriminator, UP and DOWN, and a charge pump capacitor Ccp. The main circuit may include a first branch circuit 11 and a second branch circuit 12.
The bias circuit provides a bias voltage and a bias current to a post-stage circuit. I1 is a current flowing through the PMOS transistor MP2 in the first branch circuit 11. I2 is a current flowing through the NMOS transistor MN1 of the first branch circuit 11. I1/I2 mirrors a reference current Iref in a certain proportion. MP4 is switched on or switched off by the output control signal UP from the phase frequency discriminator, while MN3 is switched on or switched off by the output control signal DOWN from the phase frequency discriminator. In a case that the signals UP and DOWN are low levels, MP4 is switched on while MN3 is switched off, Ich is a current flowing through the PMOS transistor MP4 in the second branch circuit 22, Idis is a current flowing through the NMOS transistor MN3 in the second branch circuit 22, and Idis mirrors I1 to charge the capacitor Ccp. In a case that the signals UP and DOWN are high levels, MP4 is switched off while MN3 is switched on, and Idis mirrors I2 to discharge the capacitor Ccp. In a case that MP4 and MN3 each are switched off, the capacitor is not charged or discharged, and Vcp is maintained constant.
The above circuit has an issue of current mismatch in a current mirror and an issue of charge sharing. For the issue of current mismatch in a current mirror, due to channel modulation effect, a Vds of the transistor MP3 in the PMOS current mirror does not equal to a drain-source voltage Vds of the transistor MN4 in the NMOS current mirror. For example, if Vcp (a potential at a node Y shown in FIG. 2) is high, voltages of drain electrodes of MP4 and MN3 are high and Ich<Idis. In this case, during a pulsed reset, MP4 and MN3 each will be switched on, which leads to a charge release of the capacitor Ccp, then Vcp is decreased correspondingly but not be maintained constant, which may affect a subordinate circuit. For the issue of charge sharing, the transistor MP3 of the PMOS current mirror and the transistor MN4 of the NMOS current mirror are respectively close to the power supply and the ground, the drain electrodes has certain capacitances. In this case, if the switch transistors MP4 and MP3 each are switched off, then the transistor MP3 charges the node Y to VDC and MN4 discharges a node X to zero potential. At a next phase comparison instant, if the switch transistors MP4 and MP3 each are switched on, the potential at the node X is increased while the potential at the node Y is decreased. If voltage drops on the switch transistors MP4 and MP3 are omitted, VX=VY=VCcp. In this case, a variation of VX may not always equal to a variation of VY even if CX=CY, and the difference between VX and VY is provided by Ccp, thus a jitter occurs on a voltage applied on Ccp.
It can be seen clearly from FIG. 3 that, Ich is not equal to Idis. Narrow reset pulses are introduced in the output signals UP and DOWN from the phase frequency discriminator due to a delay of an internal loop of the phase frequency discriminator. When eliminating a dead zone, the reset pulse may switch on both the PMOS switch transistor and the NMOS switch transistor. In this case, if the charging current is not equal to the discharging current, a net current flowing through the charge pump capacitor Ccp is not zero. Hence, the potential at Ccp changes fixedly in each period, and a phase error may be generated between an input and an output of the phase-locked loop to keep the phase-locked loop locking.
As shown in FIG. 4, a second existing charge pump circuit includes PMOS current mirrors MP2 and MP4, NMOS current mirrors MN3 and MN5, a PMOS switch transistor MP3, an NMOS switch transistor MN5, bias circuits MN1 and MN2, output control signals UP and DOWN from a phase frequency discriminator and a charge pump capacitor Ccp. The subject circuit may include a third branch circuit 33 and a fourth branch circuit 44. The circuit may be considered as an improvement of the first charge pump circuit in that: firstly, an operational transconductance amplifier is added, and with a feedback effect, potentials at a node X and a node Y are equal to each other, hence a charging current equals to a discharging current; and secondly, locations of switch transistors are exchanged with locations of current mirrors to address the issue of charge sharing. However, it can be seen from FIG. 5 that, Ich and Idis may change as the output voltage changes even if Ich=Idis in the charge pump circuit; therefore, the charging current and the discharging current are non-constant.